Performance Lab

Interactive models of runtime behaviour.

These are conceptual visualisations, not cycle-accurate CPU simulators. Their purpose is to expose the mechanics clearly enough that the abstraction stops lying by omission.

All labs

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The full curriculum

Reference labs and the 36-lab curriculum

41 laboratories total: the 8-lab reference tier (cache hierarchy through thread-per-core, plus JIT pipeline) and the 36-lab curriculum defined by the plab-010–plab-606 proposals — three labs (False Sharing, SPSC Ring Buffer, JIT Pipeline) belong to both, so the totals below aren't a simple sum. Status is never inferred: cards without a link haven't been built yet, and every result names its own evidence maturity before you trust a number.

Cache coherence

False sharing

Two independent counters occupy the same cache line. Every write invalidates the other core's copy, because silicon remains stubbornly literal.

Conceptual model

A simplified two-state view of MESI ownership transfer, not a cycle-accurate coherence simulation.

CPU 0 · state: Modified
CPU 1 · state: Invalid
Observe Modified → Invalid ownership transfer

Lock-free structures

SPSC ring buffer

A bounded single-producer, single-consumer queue needs ownership discipline more than a heroic number of atomics.

Conceptual model

An illustrative fixed-capacity buffer, not a benchmarked throughput/latency measurement.

0 1 2 3 4 5 6 7
head 0
tail 0
size 0
capacity = 8

HotSpot

JIT compilation pipeline

The source is only the first draft. Runtime profiling and speculative optimisation decide what eventually executes.

Conceptual model

A simplified tier progression, not a trace of an actual HotSpot compilation log.

Java source
Bytecode
Interpreter
C1 + profiling
C2 machine code
Remember: inlining, escape analysis and devirtualisation depend on code shape and profile stability. “The JIT will optimise it” is not a design.

Sources

  • Java Concurrency in Practice — Goetz et al.
  • Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A §11 (Memory Cache Control) — intel.com/sdm
  • The Java Virtual Machine Specification, Chapter 2 (Execution Engine / JIT tiers) — docs.oracle.com/javase/specs