Performance Lab
Interactive models of runtime behaviour.
These are conceptual visualisations, not cycle-accurate CPU simulators. Their purpose is to expose the mechanics clearly enough that the abstraction stops lying by omission.
Cache coherence
False sharing
Two independent counters occupy the same cache line. Every write invalidates the other core's copy, because silicon remains stubbornly literal.
CPU 0 · state: Modified
CPU 1 · state: Invalid
Observe Modified → Invalid ownership transfer
Lock-free structures
SPSC ring buffer
A bounded single-producer, single-consumer queue needs ownership discipline more than a heroic number of atomics.
0
1
2
3
4
5
6
7
head 0
tail 0
size 0
tail 0
size 0
capacity = 8
HotSpot
JIT compilation pipeline
The source is only the first draft. Runtime profiling and speculative optimisation decide what eventually executes.
Java source
Bytecode
Interpreter
C1 + profiling
C2 machine code
Remember: inlining, escape analysis and devirtualisation depend on code shape and profile stability. “The JIT will optimise it” is not a design.